GPIO and Hardware Expansion
Electrical safety first
External-header signals are 5 V-tolerant only in digital I/O mode and only while the M1 is powered. Do not drive a pin when the M1 is off. Analog-capable PA9, PA10, PC1, PC2, and PC3 are limited to VDDA + 0.3 V (about 3.6 V maximum) when used in analog mode.
- When the GPIO menu opens, controllable pins start as outputs at Low.
- Leaving the GPIO menu returns the pins to a safe state and switches off external rails.
- The 3.3 V and 5 V rails cannot be enabled at the same time.
- Use 3.3 V logic whenever the connected peripheral supports it; 5 V tolerance is a protection limit, not the default signaling voltage.
GPIO menu
| Menu item | What it does |
|---|---|
| GPIO Control | Selects a documented pin and toggles its output Low or High. |
| 3.3V power | Enables the 3.3 V rail and disables the 5 V rail. |
| 5V power | Enables the 5 V rail and disables the 3.3 V rail. |
| USB-UART bridge | Bridges USB CDC to external UART1 on PA9 TX / PA10 RX at 3.3 V, or to the internal ESP32 UART. |
External headers
The enclosure silk numbers the two groups continuously from 1 through 18. Board documentation may also refer to the groups separately as J5 pins 1–8 and J7 pins 1–10. Both numbering schemes are shown below.
| Enclosure pin | J5 pin | Signal | Documented alternate function |
|---|---|---|---|
| 1 | 1 | +5 V | — |
| 2 | 2 | PE2 | SPI4 SCK |
| 3 | 3 | PE4 | SPI4 NSS |
| 4 | 4 | PE5 | SPI4 MISO |
| 5 | 5 | PE6 | SPI4 MOSI |
| 6 | 6 | PD12 | I2C4 SCL |
| 7 | 7 | PD13 | I2C4 SDA |
| 8 | 8 | GND | — |
| Enclosure pin | J7 pin | Signal | Documented alternate function |
|---|---|---|---|
| 9 | 1 | +3.3 V | — |
| 10 | 2 | PA14 | SWCLK |
| 11 | 3 | PA13 | SWDIO |
| 12 | 4 | PA9 | UART1 TX |
| 13 | 5 | PA10 | UART1 RX |
| 14 | 6 | PC2 | ADC-capable input |
| 15 | 7 | PC3 | ADC-capable input |
| 16 | 8 | PD0 | CAN RX |
| 17 | 9 | PD1 | CAN TX |
| 18 | 10 | GND | — |
Control a pin
- Open GPIO > GPIO Control.
- Use Left / Right to select a controllable signal.
- Press Center to toggle the output between Low and High.
- Press Back when finished so the M1 can return pins and rails to their exit state.
The documented control screen includes PE2, PE4, PE5, PE6, PD12, PD13, PA14, PA13, PC2, PC3, PD0, and PD1. PA9 and PA10 are reserved for the functional USB-UART bridge.
GPIO current limits
| Limit | Value |
|---|---|
| Recommended design current | Approximately 8 mA or less per pin for reliable logic-level margins |
| Absolute maximum per pin | 20 mA sourced or sunk; do not design normal loads to this ceiling |
| Combined I/O source current | 140 mA maximum across all I/O pins |
| Combined I/O sink current | 140 mA maximum across all I/O pins |
The 20 mA per-pin and 140 mA aggregate figures are STM32H573 silicon absolute maximum ratings. Exceeding them can cause incorrect operation or permanent damage. Use external drivers for higher-current loads.
Use the USB-UART bridge
- Open GPIO > USB-UART bridge.
- Use Left / Right to select UART: TX (PA9), RX (PA10), 3.3 V for the external header or UART: ESP32 for the internal ESP32 connection.
- Press Center to start the selected bridge.
- Open the M1 USB CDC serial port on the connected computer. The default is 115200 baud, 8 data bits, no parity, 1 stop bit; supported host line-coding changes are applied to the UART.
- Press Back to stop the bridge and return to the GPIO menu.
Choose the external UART1 header or the internal ESP32 connection.
Power-rail limits
- Do not exceed 0.5 A on the 3.3 V EXT output.
- Do not exceed 0.5 A on the 5 V EXT output.
- Do not power motors, solenoids, relays, heaters, or other high-current loads directly from the M1.
- Do not feed external power back into an enabled M1 rail.
- Use a common ground between the M1 and the external circuit.
- Treat analog-capable
PA9,PA10,PC1,PC2, andPC3as approximately 3.6 V maximum when used in analog mode.
Need help? Email support@monstatek.com and include the firmware version and screen name.